CMOS process active waveguides on five layer substrates

Optical waveguides – Planar optical waveguide – Thin film optical waveguide

Reexamination Certificate

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Details

C385S130000, C385S129000, C385S132000, C385S014000, C257S083000

Reexamination Certificate

active

11214704

ABSTRACT:
A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. FIG.12shows an active waveguide formed by a standard CMOS process on a five layer substrate. The waveguide is a silicon strip loaded waveguide with a three layer core made of a silicon strip on a silicon slab with a silicon dioxide layer between the strip and slab. The active waveguide has two doped regions in the silicon slab adjacent to and on either side of the waveguide. FIG.12A is a table summarizing the elements of the waveguide of FIG.12and the CMOS transistors of FIGS.1and2, which are formed from the same materials at the same time on the same silicon substrate. In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

REFERENCES:
patent: 3462211 (1969-08-01), Nelson et al.
patent: 3970364 (1976-07-01), Gerson et al.
patent: 4787691 (1988-11-01), Lorenzo et al.
patent: 4958898 (1990-09-01), Friedman et al.
patent: 4999686 (1991-03-01), Autier et al.
patent: 5001523 (1991-03-01), Lomashevich et al.
patent: 5048907 (1991-09-01), Wickman et al.
patent: 5061030 (1991-10-01), Miyamoto et al.
patent: 5125065 (1992-06-01), Stoll et al.
patent: 5654818 (1997-08-01), Yao
patent: 5908305 (1999-06-01), Crampton et al.
patent: 6052495 (2000-04-01), Little et al.
patent: 6055342 (2000-04-01), Yi et al.
patent: 6278822 (2001-08-01), Dawnay
patent: 6400490 (2002-06-01), Hosoi
patent: 6411752 (2002-06-01), Little et al.
patent: 6553157 (2003-04-01), Schultz et al.
patent: 6760493 (2004-07-01), Pruneri et al.
patent: 6839488 (2005-01-01), Gunn, III
patent: 6917727 (2005-07-01), Gunn et al.
patent: 7010208 (2006-03-01), Gunn et al.
patent: 7072556 (2006-07-01), Gunn et al.
patent: 2003/0063885 (2003-04-01), Gunn et al.
patent: 2003/0068131 (2003-04-01), Gunn, III
patent: 2003/0190107 (2003-10-01), Walker
patent: 2 243 241 (1991-10-01), None

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