CMOS process

Details CMOS process CMOS process

1986-09-23

1988-01-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 29, 437 56, 437 57, 437147, 437148, 437931, 437933, 357 42, H01L 2122, H01L 21265

Patent

active

047176830

ABSTRACT:
A process is disclosed for fabricating complementary insulated gate field effect transistors including doped field isolation regions and optional punch through protection. In one embodiment of invention, a silicon substrate is provided which has N-type and P-type surface regions. First and second masks are formed overlying active areas of the two surface regions. A third mask is then formed overlying the first region and the first mask. P-type impurities are implanted into the second region with an implant energy which is sufficient to penetrate through the second mask but insufficient to penetrate through the third mask. A second P-type implant is performed with an implant energy insufficient to penetrate through either mask. The first implant will aid in preventing punch through while the second implant dopes the field region. A fourth mask is then formed overlying the second region and the second mask. A first N-type implant is performed at energy sufficient to penetrate through the first mask but insufficient to penetrate through the fourth mask. This implant provides punch through protection for P channel transistors to be formed later. A second N-type impurity is implanted into the surface at an implant energy insufficient to penetrate through the first mask to provided field doping. The silicon substrate is then oxidized to form a field oxide at portions of the first and second surface regions which are not covered by the first and second masks.

REFERENCES:
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patent: 4295266 (1981-10-01), Hsu
patent: 4306916 (1981-12-01), Wollesen et al.
patent: 4412375 (1983-11-01), Matthews
patent: 4435895 (1984-03-01), Parrillo et al.
patent: 4435896 (1984-03-01), Parrillo et al.
patent: 4468852 (1984-09-01), Cerofolini
patent: 4554726 (1985-11-01), Hillenius et al.
patent: 4570325 (1986-02-01), Higachi
patent: 4599789 (1986-07-01), Gasner
patent: 4613885 (1986-09-01), Haken
IEEE Transa on Electron Devices, vol.-31, No. 7, Jul. 1984, pp. 910-919, "Quadruple-Well CMOS for VLSI Technology", by John Y-T Chen.

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