CMOS preferred state power-up latch

Details CMOS preferred state power-up latch CMOS preferred state power-up latch

1998-12-04

2000-05-09

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327208, 327210, H03K 337

Patent

active

060609192

ABSTRACT:
A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.

REFERENCES:
patent: 3983543 (1976-09-01), Cordaro
patent: 3983545 (1976-09-01), Cordaro
patent: 4581552 (1986-04-01), Womack et al.
patent: 4591745 (1986-05-01), Shen
patent: 4902910 (1990-02-01), Msieh
patent: 5115146 (1992-05-01), McClure et al.
patent: 5161159 (1992-11-01), McClure et al.
patent: 5336944 (1994-08-01), Fischer
patent: 5361229 (1994-11-01), Chiang et al.
patent: 5706232 (1998-01-01), McClure et al.

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