CMOS power-up reset circuit for gate arrays and standard cells

Details CMOS power-up reset circuit for gate arrays and standard cells CMOS power-up reset circuit for gate arrays and standard cells

1984-11-20

1986-12-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307246, 307592, 307601, H03K 1722

Patent

active

046331077

ABSTRACT:
A power-up reset circuit has a first circuit for sensing a source voltage potential and generating a reset signal at an output when the source voltage potential rises above a threshold level. An input of the sensing circuit is coupled to the source voltage potential to permit a voltage at the sensing circuit's input to follow the source voltage potential during an initial rise of the source voltage potential. The power-up reset circuit further has a second circuit for sensing the source voltage potential and generating a time delayed signal at an output when the source voltage potential rises above a predetermined level. A termination circuit has an input coupled to the output of the second circuit and generates a termination signal at an output coupled to the input of the first circuit to terminate the reset signal in response to the time delayed signal. A feedback switch has an input coupled to the output of the first circuit and couples the terminating circuit to the source voltage potential in response to the reset signal and decouples the terminating circuit from the source voltage potential in response to the termination of the reset signal.

REFERENCES:
patent: 3895239 (1975-07-01), Alaspa
patent: 4001609 (1977-01-01), Sickert
patent: 4045688 (1977-08-01), Stewart
patent: 4140930 (1979-02-01), Tanaka
patent: 4409501 (1983-10-01), Eickerman et al.
patent: 4558233 (1985-12-01), Nakamori

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