CMOS power-on reset pulse generating circuit with extended reset

Details CMOS power-on reset pulse generating circuit with extended reset CMOS power-on reset pulse generating circuit with extended reset

1983-02-16

1985-12-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307354, 307579, 307267, 307594, H03K 5153, H03K 17687

Patent

active

045582335

ABSTRACT:
A source voltage buildup detecting circuit which detects, after the source is switched on, whether the source voltage is higher than a predetermined voltage and outputs a detecting signal. The source voltage buildup detecting circuit includes a complementary metal-oxide semiconductor (CMOS) inverter, a level shifting element connected between the power source and the CMOS inverter, and a voltage generating circuit connected to an input of the CMOS inverter. The level shifting element supplies a voltage lower than the source voltage to the CMOS inverter as a working voltage, and when the source voltage becomes greater than the predetermined voltage after the source voltage is switched on, the voltage generating circuit outputs a voltage higher than the threshold voltage of the CMOS inverter. When the source voltage becomes higher than the predetermined voltage, the voltage generating circuit outputs a voltage lower than the threshold voltage of the CMOS inverter.

REFERENCES:
patent: 4013902 (1977-03-01), Payne
patent: 4103187 (1978-07-01), Imamura
patent: 4140930 (1979-02-01), Tanaka
patent: 4173756 (1979-11-01), Kawagai et al.
patent: 4196362 (1980-04-01), Maehashi
patent: 4300065 (1981-11-01), Remedi et al.
patent: 4322639 (1982-03-01), Yamashiro
patent: 4405871 (1983-09-01), Buurma et al.
patent: 4409501 (1983-10-01), Eickerman et al.
Patents Abstracts of Japan, vol. 3, No. 82, Jul. 14, 1979, p. 75 E 123 & JP-A-54 60849 (Fujitsu K.K.), 16-05-1979, Abstract; figure.

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