CMOS power-on reset circuit

Details CMOS power-on reset circuit CMOS power-on reset circuit

1985-04-03

1987-01-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307363, 307272R, 307585, 307591, 307601, 307603, 307605, H03K 1722

Patent

active

046349049

ABSTRACT:
A CMOS reset circuit has a reverse biased diode and a latch for latching a p-channel enhancement mode MOSFET on during the first part of the power-on cycle. The p-channel MOSFET is part of a voltage divider which also includes a resistor. When the voltage between p-channel MOSFET and resistor reach the threshold of an n-channel enhancement mode MOSFET, the p-channel MOSFET is switched off. Reset pulses are provided through one or two inverters by a load on the latch.

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patent: 4419596 (1983-12-01), Kikuchi
patent: 4558233 (1985-12-01), Nakamori

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