CMOS power amplifier for driving low impedance loads

Details CMOS power amplifier for driving low impedance loads CMOS power amplifier for driving low impedance loads

2000-08-11

2002-05-28

Shingleton, Michael B (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including plural stages cascaded

C330S277000, C330S295000

Reexamination Certificate

active

06396352

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to analog amplifier circuits.
BACKGROUND OF THE INVENTION
A typical prior art 2-stage amplifier block diagram is shown in FIG.
1
. The circuit of
FIG. 1
includes transconductors
20
and
22
, resistors
24
-
26
, capacitors
28
-
30
, output resistance
32
, output capacitance
34
, input voltage V
in
, and output voltage V
out
. The prior art circuit of
FIG. 2
shows the last section of a prior art folded cascode input stage coupled to an output stage as used in transconductors
20
and
22
. The circuit of
FIG. 2
includes output transistors
40
and
42
, capacitors
44
and
46
, quiescent current bias network
48
, output voltage V
out
, and transistors
50
-
53
. To get maximum current drive, transistors
40
and
42
need to be very large devices. In order to not waste quiescent current, the gate-to-source voltage minus the threshold voltage (V
GS
−V
T
) of transistors
40
and
42
are set as small as possible. The maximum output current determines the size of transistors
40
and
42
. The quiescent current is set by the second stage transconductance and the total harmonic distortion (THD) level of performance at small signal levels. At very low V
GS
−V
T
the quiescent current is less controlled as transistors
40
and
42
head for subthreshold region of operation. Another problem with very low V
GS
−V
T
is that the input stage cascodes may not have the head room required for maximum gain out of the stage. This is certainly true for modern CMOS processes where the V
T
of the devices are going down, and operating voltages for systems is going down as well. Another problem is the very large parasitic capacitance of the large output transistors
40
and
42
. Typical load resistances for designs using CMOS power amplifiers are 32 Ohm all the way down to 8 ohm. With signal swings in the 4 volt range, this translates to current in the 70 mA to 250 mA range without sacrificing performance. These large power levels even with 90 Angstrom gate oxide on analog processes can result in PMOS devices sizes approaching 20,000 um (W/L). In these cases the parasitic capacitance of the output transistors
40
and
42
would be enormous, and would cause major problems with the stability of the amplifier. Using these prior art techniques, the quiescent current needed for proper operation of an amplifier of this type is very high. An amplifier of this type achieves good overall performance only at a maximum current to quiescent current ratio of 60-70. For proper operation the quiescent current level has to be such that the maximum load current is about 60-70 times the quiescent current. This does not solve the stability issue of the parasitic capacitance being very large.
SUMMARY OF THE INVENTION
A two-stage power amplifier includes: a first stage transconductor; and second stage having at least two parallel output branches supplying current to an output node, each output branch has an input coupled to an output of the first stage amplifier.

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