Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock
Patent
1984-07-11
1987-01-06
Zazworsky, John
Electrical transmission or interconnection systems
Personnel safety or limit control features
Interlock
307351, 307353, 307358, 307261, 307520, G01R 1902, G01R 1922
Patent
active
046348956
ABSTRACT:
The present invention relates to a CMOS peak detection circuit (10) which does not require a blocking diode as is used in conventional peak detection circuits. The detection circuit of the present invention comprises a comparator which functions to compare the current value of an AC input signal to a current peak value stored on a capacitor (16). The output of the comparator is connected to a NAND gate which in turn activates a CMOS transmission gate (12) disposed between the input signal line and the storage capacitor. When the current value of the input signal is greater than the current peak value stored on the capacitor, the CMOS transmission gate is turned on and the AC input signal is transferred to the storage capacitor. Alternatively, if the current value of the input signal is less than that stored on the capacitor, the NAND gate will not activate the CMOS transmission gate, and the input signal cannot pass to the capacitor. A negative peak detector can be formed merely by inverting the inputs to the comparator and resetting the storage capacitor to the positive power supply instead of the negative power supply. A tandem arrangement of a positive peak detector and a negative peak detector formed in accordance with the present invention may be utilized to determine the DC level of an AC input signal, since each detector will generate the peak positive and negative values of the input signal and the DC level is defined as the average value of these two peak values.
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AT&T Bell Laboratories
Koba Wendy W.
Zazworsky John
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