CMOS P-Well selective implant method

Details CMOS P-Well selective implant method CMOS P-Well selective implant method

1979-09-20

1981-12-22

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148187, 357 23, 357 42, 357 91, H01L 754, H01L 21265, B01J 1700

Patent

active

043069169

ABSTRACT:
A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.

REFERENCES:
patent: 4013484 (1977-03-01), Boleky
patent: 4045250 (1977-08-01), Dingwall
patent: 4081896 (1978-04-01), Dingwall
patent: 4084311 (1978-04-01), Yasuoka et al.
patent: 4104784 (1978-08-01), Klein
patent: 4139402 (1979-02-01), Steinmaier et al.
patent: 4217149 (1980-08-01), Sawazaki

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