Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-02-23
2001-03-27
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000, C326S027000
Reexamination Certificate
active
06208178
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to output buffers, and more particularly for CMOS output buffers with isolation during bus over-voltage.
BACKGROUND OF THE INVENTION
As integrated circuit (IC) device geometries shrink, lower power-supply voltages are used to prevent device failures. The standard 5-volt supply has dropped to 3 volts and below. Switching from 5 volts to 3 volts results in a 34% reduction in the electric fields carried across a device such as a complementary metal-oxide-semiconductor (CMOS) transistor. The lower power-supply voltage significantly reduces adverse side effects and power consumption and heat generation.
However, it has not been possible to convert all electronic devices to the new lower-volt standard. Thus a system designer often has to use an older 5-volt IC with a newer 3-volt IC. For example, a newer microprocessor may operate at 3 volts, while data buffers attached to that microprocessor may only be available in 5-volt IC's. In the communications field, a newer 3-volt device may have to drive a bus that is also driven by older 5-volt devices.
FIG. 1
illustrates a bus that must be driven by both 3-volt and 5-volt devices. Several drivers
10
,
14
,
16
can connect to bus
12
. However, only one of drivers
10
,
14
,
16
will be driving bus
12
at any one time. The other drivers will be in a high-impedance state. For example, when driver
14
is driving data out onto bus
12
, drivers
10
and
16
are in a high-impedance state and do not drive data out onto bus
12
. A driver in a high-impedance state only draws a small amount of current from bus
12
, otherwise it could alter the logic level appearing on bus
12
. In fact, if it draws a large current when in a high-impedance state it could even damage the driver.
Bus
12
has a low logic-level of about 0 volts but a high logic-level of 3 to 5 volts. Thus older devices such as driver
14
, which operate off a 5-volt power supply, drive bus
12
to 0 or 5 volts. Newer devices, such as driver
16
, operate off a 3-volt power supply and drive bus
12
to 0 or 3 volts. Thus a high logic-level output from driver
14
will be about 5 volts, while a high logic-level output from driver
16
is about 3 volts.
Newer 3-volt drivers such as driver
10
must be able to connect to bus
12
even when bus
12
is at 5 volts, which is 2 volts higher than the power supply of 3 volts powering driver
10
. Since bus
12
operates at high speeds, it is not feasible to mechanically disconnect a driver in a high-impedance state from bus
12
, as with a mechanical relay. Electrical circuit means are needed to isolate a driver in a high-impedance state from bus
12
.
FIG. 2
is an output buffer using CMOS transistors and gates that can be placed in a high-impedance state. A large n-channel driver transistor
20
pulls bus
12
low, to ground or 0 volts, when it is turned on. The body terminal of transistor
20
is connected to ground, as indicated by the dashed line coming from the channel of transistor
20
. Since the source of transistor
20
is also connected to ground, once the gate voltage exceeds the n-channel threshold voltage of about 0.7 volts, transistor
20
will turn on and conduct between its drain (tied to bus
12
), and its source (ground).
The gate of transistor
20
is driven by inverter
22
, which is driven by NAND gate
26
. The output of NAND gate
26
is low, and thus transistor
20
drives bus
12
low, when the enable signal EN is high and the input voltage V
IN
is high.
A large p-channel driver transistor
18
pulls bus
12
high, to the power supply or 3 volts, when it is turned on. The body terminal of p-channel transistor
18
is connected to the power supply, as indicated by the dashed line coming from the channel of transistor
18
. Since the source of transistor
18
is also connected to the power supply, once the gate voltage is less than the power supply by the magnitude of the p-channel threshold voltage of about −0.7 volts, transistor
18
will turn on and conduct between its source (the power supply), and its drain (tied to bus
12
).
The gate of p-channel transistor
18
is driven by inverter
24
, which is driven by NOR gate
28
. The output of NOR gate
28
is high, and thus p-channel transistor
18
drives bus
12
high, when the inverse enable signal {overscore (EN)} is low and the input voltage V
IN
is low. Thus V
IN
is inverted and driven out on bus
12
when the enable signals EN, {overscore (EN)} are active (1 and 0, respectively).
Isolation Difficult
Isolating a high-impedance driver using only CMOS transistors is a difficult design problem. Isolating n-channel transistor
20
of
FIG. 2
is easily accomplished by driving zero volts on its gate. The gate-to-source voltage is thus 0 volts, which is less than the n-channel threshold voltage of about 0.7 volts. Thus n-channel transistor
20
will not conduct, regardless of whether 3 volts or 5 volts is applied to bus
12
, which is coupled to the drain of transistor
20
. Since the p-well or p-substrate of n-channel transistor
20
is also connected to ground, as indicated by the body terminal or transistor
20
being tied to ground, the parasitic diode between the n+ drain and the p-substrate will be reverse biased at both 3 and 5 volts on the drain. Thus there would be only a very small leakage current from the n+ drain or the channel or n-channel transistor
20
.
However, isolating the p-channel transistor
18
when bus
12
is at 5 volts is problematic. This isolation problem of the prior art is illustrated in
FIG. 3
, which shows a cross-section of p-channel driver transistor
18
of FIG.
2
. P-channel transistor
18
has a gate
36
, a source
38
, and a body terminal
40
all tied to the power supply of 3 volts. Thus n-well
32
is at 3 volts because of the connection of the n+ well tap or body terminal
40
to the n-well
32
. The p-substrate
34
is biased to ground by a p+ substrate tap (not shown).
When bus
12
is being driven to 5 volts by another driver, little or no current should be drawn from bus
12
through p+ drain
30
as the device should be put in a high-impedance state. However, very large currents can be drawn through p+ drain
30
. Two mechanisms can draw current. First, p-channel transistor
18
will turn on and conduct through channel
41
between p+ source
38
and p+ drain
30
. P-channel transistor
18
turns on because the 5 volts on p+ “drain”
30
is 2 volts above the 3 volt gate voltage on gate
36
. Thus p+ “drain”
30
reverses roles and act as a source, while p+ “source”
38
acts as the drain, since it is at 3 volts. Thus p-channel transistor
18
is tuned on and conducts current from bus
12
to the 3-volt power supply connected to p+ “source”
38
. This can be a large current because transistor
18
is a large driver transistor that must drive the relatively high-capacitance bus
12
. Transistor
18
could draw tens of milli-amps (mA's), depending upon the size of transistor
18
.
In the second mechanism, the p+ drain
30
within n-well
32
forms a parasitic diode
42
. This diode
42
is forward biased, since p+ drain
30
is at 5 volts while n-well
32
is at 3 volts. Thus diode
42
is forward biased by 2 volts and can draw significant current. This current can trigger latch-up in a parasitic SCR formed by a parasitic PNP transistor of the p+ drain
30
as the emitter, n-well
32
base, and p-substrate
34
as a collector, and a second parasitic NPN transistor formed from n+ terminal
40
as the collector, p-substrate
34
as the base, and another n+ drain or source as the emitter (not shown) in the p-substrate.
Isolation Using Transmission Gate
A related U.S. Pat. No. 5,444,397 by Wong et al., and assigned to Pericom Semiconductor Corp. of San Jose, Calif., disclosed an isolation circuit that connected a higher-voltage output to the gate and substrate of p-channel transistors to provide bus isolation.
FIG. 4
is cross-section of a p-channel driver transistor
Auvinen Stuart T.
Lam Tuan T.
Nguyen Hiep
Pericom Semiconductor Corp.
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