CMOS output circuit with intermediate potential setting means

Details CMOS output circuit with intermediate potential setting means CMOS output circuit with intermediate potential setting means

1989-06-05

1991-01-29

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307473, 307270, 307246, H03K 1716, H03K 19024, H03K 301

Patent

active

049888889

ABSTRACT:
In a semiconductor integrated circuit device, an output MOSFET circuit includes a first N-type MOSFET and a first P-type MOSFET. The output circuit is controlled by two different control signals having two different levels to provide a signal at an output terminal at a junction between the two MOSFETs. An intermediate potential setting circuit includes a second N-type MOSFET and a second P-type MOSFET, and is followed by the output MOSFET circuit. The intermediate potential setting circuit sets the potential of the output terminal to an intermediate potential in accordance with an intermediate potential setting signal applied to the intermediate potential setting circuit prior to variation of the output. With this structure comsumption is reduced and high speed operation is made possible.

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