CMOS output circuit having controlled slope

Details CMOS output circuit having controlled slope CMOS output circuit having controlled slope

1991-06-03

1992-09-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307542, 307571, H03B 104, H03K 512

Patent

active

051480484

ABSTRACT:
Two p-channel MOS transistors are inserted in series between the positive power supply and the output terminal, whereas two n-channel MOS transistors are inserted in series between the output terminal and the negative power supply. Across the source and drain of one of the p-channel MOS transistors, a first diode is connected in parallel in the forward direction. Similarly, across the source and drain of one of the n-channel MOS transistors, a second diode is connected in parallel in the forward direction.

REFERENCES:
patent: 4626715 (1986-12-01), Ishii
patent: 4682055 (1987-07-01), Upadhyayuk
patent: 4714840 (1987-12-01), Proebsting
patent: 4970407 (1990-11-01), Patchen
patent: 5039873 (1991-08-01), Sasaki

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