CMOS output buffer with slew rate control

Details CMOS output buffer with slew rate control CMOS output buffer with slew rate control

1996-10-15

1999-03-02

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

327384, 327112, 327170, 326 27, 326 58, 326 87, H03K 1716, H03K 190948, H03K 3013

Patent

active

058776478

ABSTRACT:
An output buffer 10 of an integrated circuit controls the slew rate of an output signal in order to minimize electro-magnetic interference. Transient current delay circuits 132 and 134 provide a delay between turning off pull down circuit 122 and turning on pull up circuit 124, and vice versa, in order to assure that driver overlap does not occur. Pull up circuit 124 selectively switches a plurality of output transistors P(n) in order to control the rise time of an output signal. Likewise, pull down circuit 122 selectively switches a plurality of output transistors N(n) in order to control the fall time of an output signal so that current spikes on supply lines to output buffer 10 are reduced or eliminated.

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patent: 5537060 (1996-07-01), Baek
patent: 5568062 (1996-10-01), Kaplinsky
patent: 5708386 (1998-01-01), Chow

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