Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Patent
1995-04-06
1998-05-19
Gaffin, Jeffrey A.
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
361111, 361118, H02H 900
Patent
active
057543801
ABSTRACT:
An ESD protection circuit for use in a CMOS output buffer circuit has been disclosed. The ESD protection circuit provides a high ESD failure threshold in a small layout area to protect the output buffer against ESD failure. The output buffer includes a pull-up PMOS device and pull-down NMOS device whose common drain is connected to an output pad. The source of the PMOS device is connected to VDD and the source of NMOS device is connected to VSS. The ESD protection circuit is formed by a PTLSCR device and an NTLSCR device. The PTLSCR (NTLSCR) is formed by inserting a short-channel thin-oxide PMOS (NMOS) device into a lateral SCR structure. These MOS devices reduce the turn-on voltage of the lateral SCR to the snapback breakdown voltage of the MOS rather than the original switching voltage of the SCR. The ESD protection circuit also includes two parasitic diodes D.sub.p between output pad and VDD and D.sub.n between output pad and VSS. The four modes of ESD, PS, NS, PD and ND, are one-by-one protected by NTLSCR, Dn, Dp and PTLSCR, respectively.
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Ker Ming-Dou
Wu Tain-Shun
Gaffin Jeffrey A.
Industrial Technology Research Institute
Jackson Stephen
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