CMOS output buffer protection circuit

Details CMOS output buffer protection circuit CMOS output buffer protection circuit

1998-04-28

1999-09-14

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327318, 327319, H03L 500

Patent

active

059528664

ABSTRACT:
A low voltage CMOS output buffer protection circuit is configured to protect an associated output buffer from any high voltage signals (e.g., 5V) that may appear along a signal bus line. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). An on-chip reference voltage generator is used to provide a reference voltage VDD2 that will be essentially equal to VDD as long as VDD is present. When VDD is not present, VDD2 will track the signal appearing along the signal bus (PAD), remaining at least two diode drops below the PAD voltage.

REFERENCES:
patent: 5751179 (1998-05-01), Pietruzynski et al.
patent: 5801569 (1998-05-01), Pinkham

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