CMOS output buffer having improved noise characteristics

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307270, 307451, 307579, H03K 19094, H03K 19003

Patent

active

047315539

ABSTRACT:
A CMOS output buffer circuit which as improved noise characteristics is disclosed. The circuit has two stages, one having relatively fast response time for causing the output node to make a quick logic transition, and the other stage for providing steady-state drive of the output node. The transistors in the transition-driving stage are driven from power supply and reference supply nodes which are isolated from the power supply and reference supply nodes of the steady-state stage. For a low-to-high transition, the driving transistor in the steady-state stage, being p-channel, drives the output node to a full power supply level, which causes the driving transistor in the transition-driving stage to turn off, isolating the two power supply nodes of the two stages from one another. For a high-to-low transition, a feedback circuit serves to turn off the pull-down transistor of the transition-driving stage in order to isolate the two reference supply nodes of the two stages from one another. The steady-state stage is delayed, so that the noise from the initial transition does not appear at the power supply and reference supply nodes of the steady-state stage. The circuit also operates so that the output node can be put into a high-impedance state, allowing for common input/output utilization of the circuit.

REFERENCES:
patent: 4329600 (1982-05-01), Stewart
patent: 4477741 (1984-10-01), Moser, Jr.
patent: 4553043 (1985-11-01), Parker
patent: 4626712 (1986-12-01), Ozawa
patent: 4638187 (1987-01-01), Boler et al.
Walters, Jr. et al., "LAN System Interface Chip with Selectable Bus Protocols", 1985 IEEE ISSC Conference, pp. 190-191.

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