CMOS output buffer circuit with less noise

Details CMOS output buffer circuit with less noise CMOS output buffer circuit with less noise

1992-02-12

1994-08-02

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307270, 307443, H03K 19092, H03K 1716

Patent

active

053348893

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to an output buffer circuit, and more particularly relates to an output buffer circuit well adapted for use in a semiconductor integrated circuit to reduce noise.
It is generally required for an output buffer circuit incorporated in a semiconductor integrated circuit to be able to drive a load of a large capacity, which is connected to the output terminal of the circuit, at a high speed. High speed driving by an output buffer circuit of a high current drive capability, however, causes abrupt flow of a large current in the power source and earth lines at the moment of charge-up or discharge, thereby inducing undesirable noises in these lines. In particular in the case of a semiconductor integrated circuit, generation of such noises causes a serious problem since its input signal level and output voltage discrimination level are both close to the earth level.
It is proposed in Japanese Laid-open Patent No. 60-62725 to interpose a Miller capacitance between the input and output terminals of an output inverter circuit in an attempt to suppress generation of such undesirable noises.
The output buffer circuit of this earlier proposal is, however, quite unsuited for high speed operation since the Miller capacitance included therein slows the rise and fall of a signal wave form.


SUMMARY OF THE INVENTION

Thus, it is the primary object of the present invention to provide an output buffer circuit capable of suppressing generation of noises without degrading its high speed operation.
It is another object of the present invention to provide an output buffer circuit having a constant output response time regardless of changes in process conditions such as temperature, power source and variations in manufacture.
In accordance with one aspect of the present invention, an output buffer circuit comprises an output terminal; a first transistor connected between a first power source terminal and the output terminal for performing electric connection of the first power source terminal to the output terminal over a first prescribed period; a second transistor connected between a second power source terminal and the output terminal and having a control terminal which controls electric connection between the second power source terminal and the output terminal; control means connected to the control terminal of the second transistor for generating a first control signal with a first logic level during the first prescribed period and further generating the first control signal with a second logic level during a second prescribed period which follows the first prescribed period; delay means for receiving the first control signal and for generating, on receipt of the first control signal with the second logic level, a delay signal with the second logic level at a timing of a prescribed delay time after reception; and control signal supply means for supplying, on receipt of the first control signal and the delay signal, the second control signal to the control terminal in such a manner that, during the delay time after the first prescribed period, the level of the second control signal gradually shifts from the first towards the second logic level whereas, after receipt of the delay signal, the level of the second control signal relatively swiftly shifts to the second logic level.
In accordance with the second aspect of the present invention, an output buffer circuit comprises an output terminal; a first switch connected between a first power source terminal and the output terminal for performing electric connection of the first power source to the output terminal over a first prescribed period; a first field effect transistor (hereinafter described as an FET) having a first electrode connected to a second power source terminal, a second electrode connected to the output terminal, and a control electrode; a second FET provided with a first electrode connected to the second electrode of the first FET, a second electrode, and a control electrode; a capacitor connected betwee

REFERENCES:
patent: 5124579 (1992-06-01), Naghshineh
patent: 5194764 (1993-03-01), Yano et al.

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