Amplifiers – With periodic switching input-output
Reexamination Certificate
2000-09-08
2002-09-24
Nguyen, Patricia (Department: 2817)
Amplifiers
With periodic switching input-output
C330S051000, C330S253000, C327S124000
Reexamination Certificate
active
06456159
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to operational amplifiers and in particular to CMOS operational amplifiers, and is more particularly directed toward small geometry CMOS operational amplifier architectures suitable for implementation in deep sub-micron processes.
BACKGROUND OF THE INVENTION
An op amp (operational amplifier) architecture is desirable which is suited to current and foreseeable future generations of small geometry CMOS (complementary metal-oxide-semiconductor), manufactured economically in high volume for digital circuitry. Modern deep sub-micron (DSM) processes have gate lengths much less than one micron. DSM scaling also requires scaling the gate oxide thickness which requires scaling the supply voltage: for example, from 0.6 &mgr;m (microns) at 5 volts down to 0.13 &mgr;m at 1.0 volt.
The conventional op amp, illustrated in
FIG. 1
in block diagram form, and generally depicted by the numeral
100
, comprises two gain stages. The first functions as a differential transconductance (g
m
) stage
101
and the second as an integrator
103
, separated by a differential to single-ended converter
102
. The conventional op amp
100
is illustrated in more detail in FIG.
2
.
As shown in
FIG. 2
, the g
m
stage
101
comprises a differential pair
201
,
202
with a single current source “tail”
203
(both typically, and as an example, n-type insulated-gate field effect transistors), and two current source loads
204
,
205
(typically, and as an example, provided by p-type transistors). By selecting an output
206
from only one of the differential input stages, differential to single-ended conversion is accomplished.
This single-ended output
206
is then applied to the integrator stage
103
. In the implementation shown, the integrator
103
includes a p-type output transistor
207
with a current source tail
210
, and Miller capacitor
208
. A nulling resistor
209
has been added for the sake of stability. This configuration requires the negative supply to exceed the most negative input signal voltage by one V
t
plus one saturation voltage, and the positive supply to exceed the most positive input signal voltage by one saturation voltage less one V
t
. V
t
is the threshold voltage of the MOS transistors
201
,
202
above which conduction occurs.
In the conventional op amp implementation, the integrator comprises an inverter and Miller capacitor. In DSM CMOS, the gain of a simple inverter is low, so it is usually necessary to cascode both active devices. The supply voltage in total must therefore exceed the maximum signal swing by four saturation voltages. Consequently, this architecture is difficult to implement where the supply voltage is constrained by DSM processing.
The DSM CMOS technology also suffers from DC and low frequency mismatching and noise, resulting in the amplifier described above having poor offsets and noise performance. To condition signals from a high impedance source it is desirable to have an op amp with a low voltage offset (V
os
) and low input bias current (I
b
). Op amps with bipolar input devices, especially laser trimmed, have a low V
os
but high I
b
. Op amps having JFET (junction field-effect transistor) input devices, even if laser trimmed, have a low I
b
but high V
os
, while op amps using CMOS input devices, as noted above, have lower I
b
but higher and less stable V
os
than JFET or bipolar op amps. Bipolar and JFET technologies, especially when laser trimmed, are expensive and incompatible with low cost digital circuitry.
It is known in the art that these shortcomings may be reduced by chopping the g
m
stage. This is conventionally done at a low frequency, for example 10 kHz, and such amplifiers are generally used only with low bandwidth signals. Chopping may be viewed as modulating the input signal up to an amplitude modulation of a carrier frequency, amplifying the AC (alternating current) signal at the carrier frequency, and demodulating it back to a DC (direct current) signal. The demodulated signal then contains the DC offset of the amplifier modulated up to an amplitude modulation of the carrier frequency, which must subsequently be removed by filtering. At a low carrier frequency, this filtering requires large components that are difficult to integrate and that limit the signal bandwidth.
An improved chopping technique provides for greater signal bandwidth by having two amplifiers. The low frequency and high frequency components of the signal are separated; the LF (low frequency) component may be amplified by a LF chopped CMOS op amp with low V
os
and low I
b
, while the HF (high frequency) component may be amplified by a parallel wide-band amplifier. The two components are then recombined. However, this approach requires two amplifiers and still requires large low-frequency filtering components.
An alternative approach is to use a single chopped CMOS op amp with an increased modulation frequency on the order of many megahertz. A disadvantage of this approach is that the modulating switches must be made relatively large, and, due to inevitable manufacturing tolerances and resultant dimensional mismatches, these switches induce a large offset voltage and input bias current, partly nullifying the original purpose of the design.
Consequently, a need arises for an op amp with a low V
os
and low I
b
that may be manufactured using low-cost digital-compatible CMOS technology.
SUMMARY OF THE INVENTION
These needs and others are addressed by the improved CMOS op amp of the present invention, which, in one embodiment, provides a chopped CMOS op amp implemented in a deep sub-micron process. The input signal is modulated to an amplitude modulation on a high frequency carrier, where the carrier frequency may, for example, be 100 MHz. The modulator preferably comprises CMOS switches, which function as intended even when the signal swing is rail-to-rail. After modulation, the signal is AC, and may thus be capacitively coupled (with small integrated capacitors due to the high modulation frequency) and level shifted to any convenient DC level.
The differential input stage (g
m
stage) may be implemented with simple inverters with any supply voltage exceeding just two saturation voltages plus only a small allowance for the small AC voltage excursion. This g
m
stage may be implemented with a single inverter, although a higher g
m
(and thus enhanced slew rate and reduced distortion) may be obtained by having two inverters: the first functions as a voltage gain stage, whose gain multiplies up the g
m
of the second stage. To maintain overall loop stability, the propagation delay through this voltage gain stage must be very low; however, this stage must be operated at high current levels to achieve low input thermal noise, and it will thus naturally have low delay.
Amplifying the signal as an AC modulation has the further advantage that DC offsets and low frequency noise in the amplifying devices, characteristic of DSM CMOS, are removed at the demodulator. The primary source of offsets and associated low frequency noise are then the modulating switches. These offsets are, in a practical implementation, already lower than would be obtained by DC amplification in DSM CMOS.
Advantages of using a modulation frequency that is as high as the technology permits (e.g., 100 MHz in 0.35 &mgr;m 3.3 v technology) are that AC coupling and filtering of the AC signal may be performed by small on-chip components, and the input signal frequency may be as high as 1 MHz, for example.
To accomplish this, the integrator is implemented with inverters which are not cascoded, and the required gain, matching or indeed exceeding that which may be achieved with one cascoded inverter (as would be conventional), is achieved by using three inverters. Such an integrator is inherently unstable: it forms a ring oscillator. It is therefore stabilized by nesting a second compensation capacitor within the outer ring of the integrator, with a Miller capacitor around the second inverter. This configuration is stable.
This architecture is suite
Analog Devices Inc.
Nguyen Patricia
Wolf Greenfield & Sacks P.C.
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