CMOS on-chip precision voltage reference scheme

Details CMOS on-chip precision voltage reference scheme CMOS on-chip precision voltage reference scheme

1995-12-29

2001-09-11

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S540000, C327S156000, C327S157000

Reexamination Certificate

active

06288602

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit technology in general, and more particularly, to circuits that generate reference voltages in said integrated circuit technology.
2. Prior Art
The rapid improvements in the development and use of the CMOS technology has created a need for a process friendly reference voltage generating system. As is used in this application, process friendly means using the regular or standard CMOS process to generate a desired circuit component, module or system. In particular, a process friendly reference voltage generating system is realized from use of a regular or conventional CMOS process.
The generation of a reference voltage using modified CMOS processes has been done in the prior art. Known prior art implementations use two FETs with different threshold voltages. The prior art also teaches that the device threshold voltages can be controlled by ion implementation and/or varying the geometries of the devices. The examples of the prior art teachings are set forth in U.S. Pat. Nos. 4,305,011; 4,442,398; 4,464,588; 4,100,437; 4,327,320; 4,472,871; 4,453,094 and 4,742,292.
Even though the prior art teachings are a step in the right direction in that they suggest using, to the extent possible, a single process for providing the reference voltage generation, they fall short of intended goals in that none uses the standard or conventional CMOS process to provide a reference voltage generation. Stated another way, additional process steps, not common to the standard CMOS process, or devices not commonly used in CMOS technology, are required to generate the prior art reference voltage generators. The additional process steps and devices increase product cost.
BRIEF SUMMARY OF THE INVENTION
It is therefore the main object of the present invention to provide a reference voltage generator which is totally fabricated with a standard CMOS process.
It is a more particular object of the present invention to generate the reference voltage generation with components available in the CMOS technology.
The reference voltage generator can be implemented as part of a VLSI chip or module, system or the like. The reference voltage generator is comprised of a PLL in which the output from the loop filter circuit is the precise reference voltage. The VCO input is coupled to the loop filter circuit and the VCO output is coupled to the frequency adjustment means comprised of a divide by M and a divide by N circuits, M and N being integers, a digital control logic arrangement coupled to the divide circuits and a device, such as a clock, for providing a signal at a predetermined frequency coupled to one of the divide circuits.
The foregoing features and advantages of this invention will be more fully described in the accompanying drawings.


REFERENCES:
patent: 3903469 (1975-09-01), Ravas
patent: 4507572 (1985-03-01), Hashimoto et al.
patent: 4862015 (1989-08-01), Grandfield
patent: 4881244 (1989-11-01), Haug
patent: 4929882 (1990-05-01), Szepesi
patent: 4958086 (1990-09-01), Wang et al.
patent: 4973857 (1990-11-01), Hughes
patent: 4987387 (1991-01-01), Kennedy et al.
patent: 5016221 (1991-05-01), Hamstra
patent: 5089723 (1992-02-01), Davis et al.
patent: 5142696 (1992-08-01), Kosiec et al.
patent: 5144156 (1992-09-01), Kawasakai
patent: 5170297 (1992-12-01), Wahler et al.
patent: 5172018 (1992-12-01), Colandrea et al.
patent: 5173665 (1992-12-01), Norimatsu
patent: 5187384 (1993-02-01), Blöckl
patent: 5206553 (1993-04-01), Imai et al.
patent: 5208546 (1993-05-01), Nagaraj et al.
patent: 5256980 (1993-10-01), Itri
patent: 5391979 (1995-02-01), Kajimoto et al.

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