CMOS on-chip four-LVTSCR ESD protection scheme

Details CMOS on-chip four-LVTSCR ESD protection scheme CMOS on-chip four-LVTSCR ESD protection scheme

1995-04-06

1996-11-05

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361111, 361118, H02H 900

Patent

active

055723942

ABSTRACT:
An on-chip ESD protection circuit for use in a submicron CMOS integrated circuit (IC) has been disclosed. The ESD protection circuit provides a high ESD failure threshold in a small layout area to protect the input stage of the submicron CMOS IC against ESD failure. The ESD protection circuit is formed by a PTLSCR1, PTLSCR2 devices and an NTLSCR1, NTLSCR2 devices. The PTLSCR1 or PTLSCR2 (NTLSCR1 or NTLSCR2) is formed by inserting a short-channel thin-oxide PMOS (NMOS) device into the lateral SCR structure. These MOS devices are used to reduce the turn-on voltage of the lateral SCR to below the gate-oxide breakdown voltage of the CMOS devices in the input stage. Thus these PTLSCR1, PTLSCR2, NTLSCR1 and NTLSCR2 devices perform full ESD protection without additional secondary ESD protection elements. The four modes of ESD, PS, NS, PD and ND, are one-by-one protected by the NTLSCR1, NTLSCR2, PTLSCR1 and PTLSCR2 devices respectively.

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