CMOS on-chip ESD protection circuit and semiconductor structure

Details CMOS on-chip ESD protection circuit and semiconductor structure CMOS on-chip ESD protection circuit and semiconductor structure

1992-04-02

1993-01-26

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

257360, 257141, 257133, H01L 21265

Patent

active

051822202

ABSTRACT:
A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply termiamls, V.sub.DD and V.sub.SS. The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated component are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.

REFERENCES:
patent: 4631567 (1986-12-01), Kokado et al.
patent: 5012317 (1991-04-01), Roontre
patent: 5086242 (1992-02-01), Heidman et al.
Chatterjee et al., 1990 Symposium on VLSI Techn., IEEE (1990), pp. 75-76.
Rountree, IEDM (1988), pp. 580-583.

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