CMOS on-chip ESD protection circuit and semiconductor structure

Details CMOS on-chip ESD protection circuit and semiconductor structure CMOS on-chip ESD protection circuit and semiconductor structure

1992-11-18

1994-02-22

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361111, 361118, H02H 900, H02H 322

Patent

active

052893340

ABSTRACT:
A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply terminals, V.sub.DD and V.sub.SS. The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated components are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.

REFERENCES:
patent: 4484244 (1984-11-01), Avery
patent: 4855620 (1989-08-01), Duvvury et al.
Chatterjee et al., 1990 Symposium on VLSI Techn., IEEE (1990), pp. 75-76.
Rountree, IEDM (1988), pp. 580-583.

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