CMOS offset trimming circuit and offset generation circuit

Details CMOS offset trimming circuit and offset generation circuit CMOS offset trimming circuit and offset generation circuit

1997-07-11

2000-01-04

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

327307, H01H 3776

Patent

active

060114258

ABSTRACT:
A CMOS offset trimming circuit and offset generation circuit for obtaining the corrected optimum offset value for correcting the offset generated in the CMOS analog circuit. An offset trimming circuit comprises a flip-flop for loading a data to be used for obtaining an optimum offset value or a data to be trimmed according to an input clock, a fuse circuit for setting the circuit with a corrected optimum offset value obtained in a corresponding mode by receiving the data loaded on the flip-flop and the mode selection signal as an input signal, and a selection logic circuit for outputting a selected signal as a trimming output signal by selecting one from the group consisting of the data loaded on the flip-flop and the data output from the fuse circuit according to the operation mode.

REFERENCES:
patent: 4987327 (1991-01-01), Fernandez et al.
patent: 5325045 (1994-06-01), Sundby
patent: 5471154 (1995-11-01), Gorden et al.
patent: 5635854 (1997-06-01), Shimanek et al.
patent: 5731760 (1998-03-01), Ramirez
patent: 5808944 (1998-09-01), Yoshitake et al.
Carley, L.R., Trimming Analog Circuits Using Floating-Gate Analog MOS Memory, IEEE International Solid-State Circuits Conference, Feb. 15, 1989, pp. 202-203.
Ramirez-Angulo, J., Digitally Trimmable MOS-Current Mirrors for High Precision Applications, IEEE, 1993, pp. 974-977.

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