CMOS off-chip driver circuits

Details CMOS off-chip driver circuits CMOS off-chip driver circuits

1990-12-14

1992-09-01

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072962, 307482, 307475, H03K 1920, H03K 301

Patent

active

051441659

ABSTRACT:
Output driver circuits which do not require two stacked PMOS pull-up transistors in order to interface a lower on-chip supply voltage with a higher voltage off-chip bus provide a significant savings in chip area for DRAMs. According to a first embodiment, an on-chip pump circuit generates the necessary voltage to interface to the external bus. A second embodiment detects and compares the external bus voltage to the on-chip V.sub.DD during tri-state. The higher voltage between the bus and V.sub.DD is used to control the PMOS pull-up device properly. A third embodiment is a hybrid of the first and second embodiments. The external bus is compared to V.sub.DD as in the second embodiment, but a higher-than-V.sub.DD voltage is generated on-chip as in the first embodiment. This on-chip generated voltage is used to control the PMOS pull-up device instead of the bus voltage when the bus voltage is higher than V.sub.DD.

REFERENCES:
patent: 4217502 (1980-08-01), Suzuki et al.
patent: 4769784 (1988-09-01), Doluca et al.
patent: 4782250 (1988-10-01), Adams et al.
patent: 4963766 (1990-10-01), Lundberg

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