CMOS off-chip driver circuit

Details CMOS off-chip driver circuit CMOS off-chip driver circuit

1999-09-16

2001-03-06

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S534000, C327S537000, C326S017000, C326S081000

Reexamination Certificate

active

06198316

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates in general to off-chip driver circuits, and, in particular, to an improved CMOS off-chip driver circuit. Still more particularly, the present invention relates to an improved CMOS off-chip driver circuit designed for operation in a lower supply voltage environment than the circuit to which the output of the off-chip driver circuit is connected.
2. Description of the Related Art:
Reduced scaling or shrinking of the geometries of devices used in integrated semiconductor circuit technology for forming denser circuits has required voltage supply sources to provide lower voltages than the heretofore generally accepted standard supply voltage of 5 volts so as to avoid a voltage breakdown in the smaller devices. During the transition from 5 volt supplies to the lower voltage supplies of 3.3 to 3.6 volts, a mix of circuits is being utilized wherein some of the circuits have been designed for use with standard 5 volt supplies while other circuits have been designed for use with the lower 3.3 to 3.6 volt supplies. In general, the geometries of memory circuits are reduced at a faster rate than are the geometries of logic circuits which are coupled to the memory circuits. In particular, CMOS random access memories are currently being designed in the 3.3 to 3.6 voltage supply technology, whereas logic circuits, such as those of transistor—transistor logic (TTL) type, which receive the output or data from the memories, are still being designed in a 5 volt supply technology.
Off-chip driver circuits are commonly used to allow such integrated circuits operating at different power supply voltage levels to communicate with each other. Problems encountered by output drivers and addressed by various prior art circuits have included: excessive voltage stress on thin oxide layers of some of the driver devices, and undesirable current leakage paths causing high power dissipation, and at times, CMOS latchup problems.
One such prior art driver circuit is taught by U.S. Pat. No. 5,151,619, of common assignee, entitled “CMOS Off Chip Driver Circuit” which is incorporated herein by reference. The schematic of the '619 circuit is depicted at FIG.
1
. The prior art circuit operates in an active (driving) mode or a high-impedance (receiving) mode. In the active driving mode, initiated by causing both inputs to have the same polarity (i.e. both high or both low), the circuit drives either a CMOS low (0 V) to a CMOS high output voltage transition or a high to low output voltage transition. In the high-impedance mode, initiated by causing node IN′ to be low while node IN is high, the driver looks like a high impedance to the next circuit stage which is normally powered by a higher voltage supply (i.e. 5 V). The thrust of the prior art circuit is to protect the transistors within the driver from high oxide gate stress and, when in high impedance mode, to prevent leakage current from flowing from the higher supply voltage (5 V) into Vdd (3.3 to 3.6 V).
The problem with the prior art driver of '619 occurs when it transitions from a high output voltage to the high-impedance state. In order to output a HIGH voltage output Vout, both inputs IN and IN′ are LOW. In order to be in the high-impedance state, input IN′ remains LOW while input IN transitions from LOW to HIGH so as to turn off pull-up transistor
12
. However, initially, transmission of the signal is through transistors
24
and
26
to pull-up node
22
. The gate of transistor
12
is hampered because p-channel transistor
26
turns off almost immediately. The n-channel transistor
24
may shut off before it drives node
22
high enough to fully shut off pull-up transistor
12
. Transistors
24
and
26
do have some leakage in this state and will over a long period of time eventually pull node
22
high enough to shut off transistor
12
. Before transistors
24
and
26
are able to shut off transistor
12
, some other driver attached to node Vout may attempt to pull Vout low. When this happens, transistor
12
will resist the attempt by sourcing current into node Vout until the other driver is able to pull Vout low enough to turn device
26
on which then drives node
22
high, thus shutting off transistor
12
. On a shared bus, several drivers can be in this partially-on condition with the combined effect altering the transition time of the net sufficiently to cause a failure.
Therefore a need exists for an improved off-chip driver circuit which properly transitions from an active mode to a high-impedance mode.
SUMMARY OF THE INVENTION
An improved off-chip driver circuit is disclosed which will properly transition from an active mode to a high impedance mode. The circuit includes first and second input nodes for receiving a first and second input signal respectively. An input transmission gate including a p-channel transistor in parallel with an n-channel transistor to receive the first input signal is provided in the circuit. A push-pull circuit is also included which comprises the pull-up transistor disposed between a voltage supply and an output node and a first pull-down transistor disposed between ground and the output node. The pull-up transistor has a gate electrode for receiving the first input signal provided by the input transmission gate. The first pull-down transistor has a gate electrode for receiving the second input signal. A control transistor is included and is coupled between the gate electrode of the pull-up transistor and the output node. The control transistor has a gate electrode connected to a first point of reference potential. An auxiliary transistor provides coupling between the first input node and a gate electrode of the p-channel transistor for establishing and maintaining a voltage at the gate electrode of the p-channel transistor during a transition of the circuit from an active mode to a high impedance mode sufficient to provide a proper transition from the active mode to the high impedance mode. A biasing transistor is also provided having a gate electrode directly connected to the output node and coupled to the voltage supply for biasing an N-well in which the pull-up transistor, the control transistor, and the auxiliary transistor are situated.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 5151619 (1992-09-01), Austin et al.
patent: 5451889 (1995-09-01), Heim et al.
patent: 5635861 (1997-06-01), Chan et al.
patent: 5719525 (1998-02-01), Khoury
patent: 5825206 (1998-10-01), Krishnamurthy et al.
patent: 5892377 (1999-04-01), Johnston et al.
patent: 5933027 (1999-08-01), Morris et al.
patent: 5973511 (1999-10-01), Hsia et al.
patent: 6130563 (2000-10-01), Pilling et al.

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