CMOS off chip driver circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307475, 307270, 365168, H03K 19017, H03K 19096, H03K 17687, H03K 1704

Patent

active

051516195

ABSTRACT:
A CMOS off-chip driver circuit is provided which includes a P-channel pull up transistor and an N-channel pull down transistor serially arranged between a first voltage source having a supply voltage of a given magnitude and ground with the common point between the transistors forming an output terminal to which is connected a circuit including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. A first P-channel field effect transistor is connected between the output terminal and the gate electrode of the pull up transistor. A first input terminal is coupled to the gate electrode of the pull up transistor through a transmission gate including a first N-channel field effect transistor arranged in parallel with a second P-channel field effect transistor, with a gate electrode of the first N-channel transistor being connected to the first voltage source and the gate electrode of the second P-channel transistor being connected to the output terminal.

REFERENCES:
patent: 4217502 (1980-08-01), Suzuki et al.
patent: 4574273 (1986-03-01), Atsumi et al.
patent: 4585958 (1986-04-01), Chung et al.
patent: 4709162 (1987-11-01), Braceras et al.
patent: 4782250 (1988-11-01), Adams et al.
patent: 4963766 (1990-10-01), Lundberg
System Process and Design Implications of a Reduced Supply Voltage Microprocessor by R. Allmon et al. in the 1990 IEEE International Solid-State Circuits Conference, pp. 48 and 49, Feb. 14, 1990.

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