CMOS/NMOS integrated circuit with supply voltage delay variation

Details CMOS/NMOS integrated circuit with supply voltage delay variation CMOS/NMOS integrated circuit with supply voltage delay variation

1989-03-17

1990-05-01

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307481, 307594, 331 57, 331108C, H03K 1714

Patent

active

049221400

ABSTRACT:
A CMOS/NMOS integrated circuit realizes individual logic circuits with a combination of CMOS and enhancement-mode NMOS devices. The parameters of the CMOS and NMOS devices are selected such that the supply voltage dependency of the CMOS devices is offset by the supply voltage dependency of the NMOS devices. Thus, the propagation delays in the CMOS and NMOS devices, individually a function of supply voltage, remain constant for variations in the supply voltage. The logic circuits include analog-to-digital converters, adders, multipliers, flip flops and ring oscillators. The ring oscillator includes two blocks of inverters. The first block comprises CMOS inverters connected in series; the second block comprises enhancement-mode NMOS inverters connected in series. The output of the first block is connected to the input of the second block, and the output of the second block is connected to the input of the first block, thus forming a "ring" of inverters. Because the supply voltage dependency of the CMOS inverters is offset by the supply voltage dependency of the NMOS inverters, the oscillation frequency of the ring oscillator is independent of the supply voltage.

REFERENCES:
patent: 3931588 (1976-01-01), Gehweiler
patent: 4016434 (1977-04-01), De Fillippi
patent: 4072910 (1978-02-01), Dingwall et al.
patent: 4340867 (1982-07-01), Sano
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4494021 (1985-01-01), Bell et al.
patent: 4641048 (1987-02-01), Pollock
patent: 4742254 (1988-03-01), Tomisawa
patent: 4845390 (1989-07-01), Chan
"Compensation for Variation in Circuit Delay", IBM TDB vol. 28, No. 12, May 1986 pp. 5180-5182.
IEEE Journal of Solid-State Circuits, vol. SC-13, No. 5, Oct. 1978, pp. 542-548; R. W. Knepper: "Dynamic Depletion Mode": an E/D MOSFET circuit Method for Improved Performance.
IEEE Transactions on Electron Devices, vol. ED-28, No. 7, Jul. 1981, pp. 886-888; D. C. Mayer et al.: "Analysis of the Switching Speed of a Submicrometer-Gate CMOS/SOS Inverter"*Figures 1,2*.
NERE/M Record-1967, pp. 168-169, "Technology and Performance of Integrated Complementary MOS Circuits*" by T. Klein.
Microelectronics Journal, vol. 13, No. 6, 1982, "A CMOS Process for VLSI Instrumentation" by Tong Qin Yi and J. M. Robertson.

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