CMOS monolithic integrated circuit

Details CMOS monolithic integrated circuit CMOS monolithic integrated circuit

1978-05-05

1979-11-06

Wojciechowicz, Edward J.

357 23, 357 41, 357 48, H01L 2702

Patent

active

041737679

ABSTRACT:
The invention concerns CMOS integrated circuits including an arrangement to prevent regenerative bipolar current flow between complementary transistors in the circuit.
In one particular form, the invention provides a CMOS inverter comprising an N-type substrate in which is formed a P-channel MOS transistor together with a P-type well having therein an N channel MOS transistor, the drain of the P-channel transistor being connected to the drain of the N-channel transistor, and there being disposed in the N-type substrate between the said transistors, a P-type region preferably extending to the depth of said P-type well and electrically connected to the source of the N-channel transistor. The effect of the P-type region aforesaid is to preclude the likelihood of regenerative bipolar conduction becoming established, in use of the inverter, in the substrate, which bipolar conduction might otherwise cause destruction of the CMOS circuit.

REFERENCES:
patent: 3641511 (1972-02-01), Cricchi et al.
patent: 3959812 (1976-05-01), Imaizumi
patent: 3967295 (1976-06-01), Stewart

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