CMOS Microprocessor architecture

Details CMOS Microprocessor architecture CMOS Microprocessor architecture

1979-08-09

1981-11-10

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 906

Patent

active

043001955

ABSTRACT:
A CMOS microprocessor is provided having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static registers. In most cases the registers are connected to two buses. A 5 bit temporary register and an 8 bit program counter are each connected to three buses. An incrementer can provide an increment or decrement function but cannot be used to store functions. A bit code generator is connected to a data bus thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter is capable of directly transferring its contents to the 5 bit temporary register. An 8 bit low order incrementer is capable of incrementing three different registers which are an address storage register, a program counter, and a stack pointer. A 5 bit high order incrementer is also capable of incrementing three registers which are an address storage register, a program counter, and a temporary register. An ALU has a first and a second input, which because of the bus structure used, can both receive data simultaneously.

REFERENCES:
patent: 4003028 (1977-01-01), Bennett et al.
patent: 4003033 (1977-01-01), O'Keefe et al.
patent: 4021656 (1977-05-01), Caudel et al.
patent: 4050058 (1977-09-01), R. Garlic

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