CMOS memory device with improved sense amplifier biasing

Details CMOS memory device with improved sense amplifier biasing CMOS memory device with improved sense amplifier biasing

1991-03-20

1992-02-11

Epps, Georgia

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357 44, 357 45, 36518905, 36518906, 36518909, 365190, H01L 27102, H01L 27105, G11C 700

Patent

active

050879570

ABSTRACT:
A CMOS memory device has a memory cell array, formed on a substrate of a first conductive type, for storing data. The data are input and output via bit line pairs connected to the memory cell array. Sense amplifiers of the first conductive type, which are embedded in wells of a second conductive type, amplify potential differences on the bit line pairs. The sense amplifiers are connected to and driven by a sense amplifier drive signal line. The sense amplifier drive signal line also biases the wells containing the sense amplifiers, thereby preventing latch-up.

REFERENCES:
patent: 4712124 (1987-12-01), Stupp
patent: 4728998 (1988-03-01), Strain
patent: 4760035 (1988-07-01), Pfleiderer et al.
patent: 4935799 (1990-06-01), Mori et al.
patent: 4965651 (1990-10-01), Wagner
patent: 5023689 (1991-06-01), Sugawara

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