CMOS memory cell with gate oxide of both NMOS and PMOS transisto

Details CMOS memory cell with gate oxide of both NMOS and PMOS transisto CMOS memory cell with gate oxide of both NMOS and PMOS transisto

1995-04-21

1997-01-21

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518508, 36518529, 257315, G11C 1604, H01L 29788

Patent

active

055965245

ABSTRACT:
A CMOS memory cell including a PMOS transistor and an NMOS transistor having a common floating gate with a gate oxide region of both the NMOS and PMOS transistors providing a tunneling window for program and erase. The PMOS and NMOS transistors of the CMOS memory cell are biased so that only the PMOS transistor is utilized during programming and only the NMOS transistor is utilized during erase to prevent depletion of the substrate beneath the tunneling oxide regions. The CMOS memory cell further includes a separate PMOS pass transistor for supplying a program voltage to the source of the PMOS transistor underlying the common floating gate, so that an NMOS threshold does not have to be added to the program voltage.

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