CMOS memory cell having an electrically floating storage gate

Details CMOS memory cell having an electrically floating storage gate CMOS memory cell having an electrically floating storage gate

1983-09-01

1987-08-11

Edlow, Martin H.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 235, 365181, H01L 2978

Patent

active

046865586

ABSTRACT:
An electrically programmable memory cell contains a source-drain series arrangement of a field-effect select transistor arrangement and a complementary pair of memory transistors arranged between a first bit line and a second bit line. The pair of memory transistors comprises a common electrically floating storage gate and a common control gate which is connected to one programming line. Each of the electrodes of the select transistors is connected to the row selecting line associated therewith. The drain regions which are connected to one another, are lead to a read line. The memory cell according to the invention permits reading without requiring any significant DC power, and programming by using the complete programming voltage as available.

REFERENCES:
patent: 4016588 (1977-04-01), Ohya et al.
patent: 4037242 (1977-07-01), Gosney
patent: 4112506 (1978-09-01), Zibu
Johnson, W. S., Perlegos, G., Renninger, A., Kuhn, G., and Ranganath, T. R., "A 16Kb Electrically Erasable Nonvolatile Memory", IEEE International Solid-State Circuits Conference Digest, 1980, pp. 152-153.
Stewart, R. G., and Plus, D., "A 4Ons CMOS E.sup.2 PROM", IEEE International Solid-State Circuits Conference Digest, 1982, pp. 110-111.
Medwin, L. B. and Ipri, A. C., "FACMOS EAROM", RCA Technical Notes, No. 1185, Jun. 1977, pp. 1-4.

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