CMOS memory cell array

Details CMOS memory cell array CMOS memory cell array

1992-09-30

1994-09-27

Thomas, Tom

Fishing, trapping, and vermin destroying

437 43, 437 48, 437 69, 437 70, H01L 2170

Patent

active

053507061

ABSTRACT:
A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.

REFERENCES:
patent: 4151021 (1979-04-01), McElroy
patent: 4267632 (1981-05-01), Shappir
patent: 5019527 (1991-05-01), Ohshima et al.
patent: 5045489 (1991-09-01), Gill et al.
patent: 5081056 (1992-01-01), Mazzali et al.
patent: 5120671 (1992-06-01), Tang et al.

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