CMOS low-voltage four-quadrant multiplier

Details CMOS low-voltage four-quadrant multiplier CMOS low-voltage four-quadrant multiplier

1995-07-26

1997-08-12

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

327356, 327116, 327119, 455333, G06F 744

Patent

active

056569645

ABSTRACT:
A four-quadrant multiplier, which is composed of CMOS transistors and suited to applications of low-voltage operation. It includes a first MOS transistor operated in the linear region; a second MOS transistor operated in the linear region and having the same transconductance value as that of the first MOS transistor; a first buffer means receiving the first input signal and maintaining a definite voltage difference between the first input signal and the drain of the first MOS transistor as well as a definite current difference between the negative terminal of the output port and the drain of the first MOS transistor; a second buffer means receiving the second input signal and maintaining the definite voltage difference between the second input signal and the connected terminal of the sources of the first MOS transistor and the second MOS transistor; a third buffer means receiving the first input signal and maintaining the definite voltage difference between the first input signal and the drain of the second MOS transistor as well as a definite current difference between the positive terminal of the four-quadrant multiplier and the drain of the second MOS transistor; a first load coupled between the negative terminal of the four-quadrant multiplier and the high voltage source; and the second load having a same load value as the first load and coupled between the positive terminal of the four-quadrant multiplier and the low voltage source.

REFERENCES:
patent: 3838262 (1974-09-01), Van De Plassche
patent: 4546275 (1985-10-01), Pena-Finol et al.
patent: 4586155 (1986-04-01), Gilbert
patent: 5397931 (1995-03-01), Bayer

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