CMOS low-power TTL-compatible input buffer

Details CMOS low-power TTL-compatible input buffer CMOS low-power TTL-compatible input buffer

1985-06-17

1987-04-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307446, 307279, 307570, 307585, 307264, 323317, H03K 3286, H03K 3353, H03K 1704, H03K 17687

Patent

active

046563741

ABSTRACT:
A CMOS buffer is disclosed having a reference potential that provide TTL logic response. The circuit is configured to draw substantially zero current. A reference potential generator develops a potential that is one N channel transistor threshold above about 1.2 volts for TTL compatibility. A single reference potential generator will provide a potential for a plurality of buffers so that its dissipation is low and is shared among the buffers. The result is a low power buffer circuit that is compensated for variations in supply voltage, temperature and device parameters.

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patent: 4450371 (1984-05-01), Bismarck
patent: 4453094 (1984-06-01), Peil et al.
patent: 4471242 (1984-09-01), Noufer et al.
patent: 4486670 (1984-12-01), Chan et al.
patent: 4507573 (1985-03-01), Nagano

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