CMOS Logic circuits with all pull-up transistors integrated in s

Details CMOS Logic circuits with all pull-up transistors integrated in s CMOS Logic circuits with all pull-up transistors integrated in s

1983-01-18

1986-02-25

Heyman, John S.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307200B, 307453, 307577, 307584, H03K 17687

Patent

active

045729727

ABSTRACT:
An integrated circuit chip with a preferred ground structure and including only pull-down transistors (on-chip) is operated by means of an off-chip pull-up transistor arrangement for precharging the data bus to logic high. The arrangement exhibits relatively low noise characteristics allowing relatively high frequency operation without generating noise voltages which exceed FET threshold voltages.

REFERENCES:
patent: 3754170 (1973-08-01), Tsuda et al.
patent: 3832575 (1974-08-01), Dasgupta et al.
patent: 3974404 (1976-08-01), Davis
patent: 4002928 (1977-01-01), Goser et al.
patent: 4045684 (1977-08-01), Eads et al.
patent: 4198648 (1980-04-01), Nishizawa
patent: 4223277 (1980-09-01), Taylor et al.

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