CMOS logic circuit with single clock pulse

Details CMOS logic circuit with single clock pulse CMOS logic circuit with single clock pulse

1985-07-08

1987-09-08

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307481, 307594, 307595, 307601, 307602, 307605, H03K 19096, H03K 19003, H03K 1920, H03K 17284

Patent

active

046926372

ABSTRACT:
A dynamic, multistage CMOS logic circuit is driven with a single source of clock pulses. The clock pulses operate odd-numbered stages. A static delay circuit provides clock pulses to even-numbered stages. The dynamic and static circuits are designed according to a discipline that guarantees the elimination of race conditions in the dynamic circuit despite the presence of uncontrollable variations in pullup and pulldown delays in the fabrication process.

REFERENCES:
patent: 3852625 (1974-12-01), Kubo
patent: 3943377 (1976-03-01), Suzuki
patent: 4104860 (1978-08-01), Stickel
patent: 4250406 (1981-02-01), Alaspa
patent: 4291247 (1981-09-01), Cooper, Jr. et al.
patent: 4404474 (1983-09-01), Dingwall
"High Speed Compact Circuits with CMOS", IEEE J. Solid State Circuits, vol. SC-17, No. 3, R. H. Krambeck et al, Jun. 1982, pp. 614-619.

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