CMOS logic circuit with output coupled to multiple feedback path

Details CMOS logic circuit with output coupled to multiple feedback path CMOS logic circuit with output coupled to multiple feedback path

1990-11-06

1992-09-29

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307451, 307574, H03K 19017, H03K 190175

Patent

active

051516225

ABSTRACT:
A TTL to CMOS input buffer circuit is provided which includes a level shifting circuit including an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; and a first circuit for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and a second circuit for preventing the first circuit from interfering with a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level.

REFERENCES:
patent: 4593212 (1986-06-01), Svager
patent: 4612461 (1986-09-01), Sood
patent: 4672243 (1987-06-01), Kirsch
patent: 4698526 (1987-10-01), Allan
patent: 4829203 (1989-05-01), Ashmore, Jr.

Affiliated with

Also associated with

Rating

CMOS logic circuit with output coupled to multiple feedback path does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS logic circuit with output coupled to multiple feedback path, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS logic circuit with output coupled to multiple feedback path will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1970685