CMOS logic circuit for high voltage operation

Details CMOS logic circuit for high voltage operation CMOS logic circuit for high voltage operation

1989-06-30

1990-09-11

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 3072722, 3072965, 36518909, 365226, H03K 1710

Patent

active

049565699

ABSTRACT:
A CMOS logic circuit for converting a low voltage logic signal with a range O-VCC into a high voltage logic signal with a range O-VPP, which may be entirely made with enhancement-type transistors, comprises an additional p-channel, decoupling transistor functionally connected in series with the p-channel transistor of the CMOS circuit which is connected to the high voltage node VPP and the additional decoupling transistor is driven by a bias voltage tied to the VPP voltage and lower than the latter by a certain preset value. The so-called gated breakdown of p-channel transistors is effectively prevented and furthermore these circuits, destined to operate under a high supply voltage, may be fabricated through a normal CMOS fabrication process not requiring particular fabrication techniques for the p-channel transistors subject to gated breakdown conditions or the formation of depletion-type transistors and without the use of special circuits which require oscillator generated driving signals.

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patent: 4845381 (1989-07-01), Cuevas
patent: 4893275 (1990-01-01), Tanaka et al.

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