CMOS Logic circuit

Details CMOS Logic circuit CMOS Logic circuit

1984-06-15

1986-03-18

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307584, 307585, 307605, 307243, H03K 19017, H03K 19094, H03K 1920

Patent

active

045771243

ABSTRACT:
A CMOS logic circuit has MOSFETs of a first conductivity type in which each terminal is connected to a corresponding input terminal of the CMOS logic circuit, delay elements are inserted between the input terminals of the CMOS logic circuit and the gates of the MOSFETs of the first conductivity type, an output inverter is inserted between the remaining terminals of each of the MOSFETs of the first conductivity type and the output terminal of the CMOS logic circuit, and in which a MOSFET of a second conductivity type is inserted between the input terminal of the output inverter and a power source which is controlled by the output from the output inverter.

REFERENCES:
patent: 4091293 (1978-05-01), Ando
patent: 4390988 (1983-06-01), Best et al.
Delecki et al., "Skew Insensitive AND Circuit", IBM-TDB; vol. 17, No. 9, p. 2581; 2/1975.

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