CMOS logic circuit

Details CMOS logic circuit CMOS logic circuit

1987-12-09

1989-03-28

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 3072722, 307279, 307480, 307481, H03K 19092, H03K 19096, H03K 329, H03K 326

Patent

active

048167029

ABSTRACT:
A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.

REFERENCES:
patent: 3984703 (1976-10-01), Jorgensen
patent: 4110641 (1978-08-01), Payne
patent: 4495629 (1985-01-01), Fasio et al.
patent: 4703200 (1987-10-01), Zangara
CMOS Integrated Circuits, National Semiconductor Corp., 1975, pp. 229-241.
Fink et al, Electronics Engineers' Handbook, McGraw Hill, 1975, pp. 16.42 to 16.49.
Horowitz et al, The Art of Electronics, Cambridge University Press, 1980, pp. 162, 384-387.

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