CMOS logic cell for high-speed, zero-power programmable array lo

Details CMOS logic cell for high-speed, zero-power programmable array lo CMOS logic cell for high-speed, zero-power programmable array lo

1992-01-06

1993-12-14

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307242, 307451, H03K 19094, G06F 738

Patent

active

052705870

ABSTRACT:
A CMOS logic cell, which may be readily arrayed to construct fast, zero-power programmable array logic (PAL) devices or field-programmable logic array (FPLAs) is disclosed. The cell is constructed from first and second pairs of P-channel insulated-gate field effect transistors (IGFETs), and first and second pairs of N-channel IGFETs. Each pair of P-channel IGFETS is connected in series between an output node and V.sub.cc, while each pair of N-channel IGFETS is connected in series between the output node and V.sub.ss. The gate of one transistor of the first. P-channel IGFET pair is connected to the output of a first memory cell, while the gate of the other transistor of the same pair is connected to an input signal I; the gate of one transistor of the second P-channel IGFET pair is connected to the output of a second memory cell, while the gate of the other transistor of the same pair is connected to signal I* (the complement of input signal I). Likewise, the gate of one transistor of the first N-channel IGFET pair is connected to the output of the first memory cell, while the gate of the other transistor of the same pair is connected to signal I*; the gate of one transistor of the second N-channel IGFET pair is connected to the output of the second memory cell, while the gate of the other transistor of the same pair is connected to signal I. Each of the memory cells may be programmed to provide either a CMOS logical 1 or 0 output, and may be either nonvolatile or volatile.

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