CMOS level shifter circuit

Details CMOS level shifter circuit CMOS level shifter circuit

1991-05-02

1992-05-12

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 357 237, H03K 190175, H03K 1920

Patent

active

051130971

ABSTRACT:
A level shifter circuit has a pair of voltage buses, first and second p-channel MOS transistors and third and fourth n-channel MOS transistors. Each transistor has a gate to control conduction. The first and third transistors are connected in series between the voltage buses and the second and fourth transistors are connected in series between the voltage buses. A node between the first and second transistors is connected to the gates of the second and fourth transistors. An input signal having one of first and second levels is applied to the gate of the first transistor while the inverse of the input signal is applied to the gate of the second transistor. One voltage bus is connected through one of the second and fourth transistors in response to the first level input signal. The other voltage bus is connected the other of the second and fourth transistors in response to the second level input signal.

REFERENCES:
patent: 4618785 (1986-10-01), Van Tran
patent: 4633192 (1986-12-01), Anami
patent: 4779015 (1988-10-01), Erdelyi
patent: 4786830 (1988-11-01), Foss
patent: 4929853 (1990-05-01), Kim et al.
Digital Integrated Electronics, Herbert Haub and Donald Schilling, pp. 39-41, 1977.

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