CMOS level converter circuit with reduced power consumption

Details CMOS level converter circuit with reduced power consumption CMOS level converter circuit with reduced power consumption

1988-10-24

1990-04-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072963, 307494, 307264, H03K 19092, H03L 500

Patent

active

049202847

ABSTRACT:
In a semiconductor integrated circuit which contains, on the same chip, at least one logic circuit operating with a positive potential power and at least one logic circuit operating with a negative potential power, a level converter circuit is inserted between above logic circuits and is constituted of two series circuits each consisting of a P-channel MOSFET and an N-channel MOSFET connected in series between power lines supplied with the positive potential power and the negative potential power, and wirings to form a flip-flop circuit with each one MOSFET in respective series circuits.

REFERENCES:
patent: 4045691 (1977-08-01), Asano
patent: 4150308 (1979-04-01), Adlhock
patent: 4437171 (1984-03-01), Hudson et al.
patent: 4532436 (1985-07-01), Bismarck
patent: 4703199 (1987-10-01), Ely

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