CMOS latchup suppression by localized minority carrier lifetime

Details CMOS latchup suppression by localized minority carrier lifetime CMOS latchup suppression by localized minority carrier lifetime

1994-09-19

1995-08-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 26, 437142, 437959, 148DIG23, H01L 21265

Patent

active

054419000

ABSTRACT:
A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

REFERENCES:
patent: 3662232 (1972-05-01), Stahr
patent: 3808473 (1974-04-01), Yamashita et al.
patent: 4007297 (1977-02-01), Robinson et al.
patent: 4047976 (1977-09-01), Bledsoe et al.
patent: 4053925 (1977-10-01), Burr et al.
patent: 4082571 (1978-04-01), Gravi et al.
patent: 4107731 (1978-08-01), Naito et al.
patent: 4184897 (1980-01-01), Anthony et al.
patent: 4383268 (1983-05-01), Martinelli et al.
patent: 4762802 (1988-08-01), Parillo
patent: 4920396 (1990-04-01), Shinohara et al.
patent: 5371040 (1994-12-01), Graff et al.
Lisiak, K. P., et al., Solid State Electronics, 19 (1976) 115 "Rhodium and Iridium as Deep Impurities in Silicon".
R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits, 2nd Edition, Section 5.2, pp. 209-218, published by John Wiley (1986).
R. R. Troutman, Latchup in CMOS Technology, Kluwer Academic, Boston, 1986 (Section 6.2). TK 7871.99.M44 T76, pp. 174-181.
W. R. Dawes, Jr., and G. F. Derbenwick, Prevention of CMOS Latchup by Gold Doping, IEEE Trans. Nucl. Sci., NS-23, pp. 2027-2030 (Dec. 1976).
A. Mongro-Campero and R. P. Love, Carrier Lifetime Reduction by Argon Implantation into Silicon, J. Electrochem. Soc. 131, pp. 655-660 (Mar. 1984).
A. G. Cullis, T. E. Seidel, and R. L. Meek, Comparative Study of Annealed Neon-,Argon-, Krypton-Ion Implantation Damage in Silicon, J. Appl. Phys. 49, pp. 5188-5198 (Oct. 1978).
M. Wittmer, J. Roth, P. Revesz, and J. W. Mayer, Epitaxial Regrowth of Ne- and Kr-Implanted Amorphous Silicon, J. Appl. Phys. 49, pp. 5207-5212 (Oct. 1978).
P. Revesz, M. Wittmer, J. Roth and J. W. Mayer, Epitaxial Regrowth of Ar-Implanted Amorphous Silicon, J. Appl. Phys. 49, pp. 5199-5206 (Oct. 1978).
M. Delfino, A. Milgram, and M. D. Strathman, Epitaxial Regrowth of Silicon Implanted with Argon and Boron, Appl. Phys. Lett., 44, pp. 594-596 (Mar. 1984).
S. Aronowitz, Quantum-Chemical Modeling of Boron and Noble Gas Dopants on Silicon, J. Appl. Phys. 54, pp. 3930-3934 (Jul. 1983).
J. W. Chen and A. G. Milnes, Energy Levels in Silicon, Ann. Rev. Mater. Sci. 10, pp. 157-228 (1980).
S. Aronowitz, H. P. Zappe, and C. Hu, Effective Charge Modification Between SiO.sub.2 and Silicon, J. Electrochem. Soc. 136, pp. 2368-2370 (Aug. 1989).
D. H. Weiner, S. S. Wong, and C. I. Drowley, Oxygen Implantation for Internal Gettering and Reducing Carrier Lifetime, Appl. Phys. Lett. 50, pp. 986-988 (Apr. 1987).
S. Rathnaphanyarat, P. Renteln, C. I. Drowley, and S. S. Wong, Oxygen Implantation to Suppress Parasitic Bipolar Action in CMOS, IEEE Trans. Electron Devices 38, pp. 355-363 (Feb. 1991).
J. R. Adams and R. J. Sokel, Neutron Irradiation for Prevention of Latch-up in MOS Integrated Circuits, Nuclear and Space Radiation Effects Conf., pp. 5069-5073 Jul. 19, 1979.

Affiliated with

Also associated with

Rating

CMOS latchup suppression by localized minority carrier lifetime does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS latchup suppression by localized minority carrier lifetime , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS latchup suppression by localized minority carrier lifetime will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2181345