CMOS latching comparator

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

3072722, 307530, H03K 524

Patent

active

052452239

ABSTRACT:
A latching CMOS comparator method and circuit are disclosed. The comparator circuit includes a differential input stage and a latching stage. The input stage includes a differential amplifier (MP3,MP4) and a Moore Mirror load. The load includes a first cross-coupled amplifier pair (MN3,MN4), and a pair of diode-connected transistors (MN1,MN2) coupled in parallel to the first amplifier to control gain. The input stage devices are sized to provide a gain on the order of 10 to 20. The latch clock signal (CLK) is isolated from the input stage to avoid injected charge offset error. The second or latching stage includes a second cross-coupled transistor amplifier (MP7,MP8) coupled to the input stage to provide additional gain. The latch clock signal is provided to a digital switch (MP9,MP10) which controls gain in the second amplifier. The digital switch enables a second pair of diode-connected transistors (MP5,MP6) disposed in parallel to the latch stage amplifier pair, to reduce gain during sampling, for a total input referenced gain on the order of 60 during sampling. The digital switch disables the diode-connected transistors during latching, so that the second amplifier operates at maximum gain during latching. The digital switch circuitry isolates the latch clock signal from the latching nodes. After latching, the diode-connected devices speed recovery by clamping the latching node voltages. The latching nodes are coupled through inverters to an RS flip-flop circuit.

REFERENCES:
patent: 4441039 (1984-04-01), Schuster
patent: 4506171 (1985-03-01), Evan et al.
patent: 4697112 (1987-09-01), Ohtani et al.
patent: 4845675 (1989-07-01), Krenik et al.
patent: 4973864 (1990-11-01), Nogami
patent: 5172011 (1992-12-01), Leuthold et al.

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