CMOS latch cell including five transistors, and static flip-flop

Details CMOS latch cell including five transistors, and static flip-flop CMOS latch cell including five transistors, and static flip-flop

1983-03-23

1984-11-20

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307279, 307452, 377 68, 377 79, 377105, 377117, H03K 3356, H03K 19096, H03K 2322, G11C 1928

Patent

active

044840870

ABSTRACT:
A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node. A cross-coupled switching element comprising a second P-channel IGFET has its gate connected to the complementary data output node and is arranged to selectively connect the data storage node to the voltage supply node. A third P-channel IGFET has its channel arranged to selectively connect the data storage node to the voltage supply node when the cell is disabled. A second N-channel IGFET is arranged to selectively connect the data storage node to the data input node. A high impedance leakage current discharge path electrically connects the data storage node to the one voltage supply node, and discharges any leakage current on the data storage node. The high impedance leakage current discharge path may take a variety of forms, and need not comprise a discrete resistor.

REFERENCES:
patent: 3573498 (1971-04-01), Ahrons
patent: 3675144 (1972-07-01), Zuk
patent: 3716723 (1973-02-01), Heuner et al.
patent: 3716724 (1973-02-01), Parrish et al.
patent: 3745371 (1973-07-01), Suzuki
patent: 3812384 (1974-05-01), Skorup
patent: 3989955 (1976-11-01), Suzuki
patent: 4114049 (1978-09-01), Suzuki
patent: 4124807 (1978-11-01), Herber
patent: 4447745 (1984-05-01), Takemae et al.
RCA Datasheet, CD4013A Types, "Dual `D`-Type Flip-Flop".
RCA Datasheet, CD4015A Types, "COS/MOS Dual 4-Stage Static Shift Register".
CD4006A Types and CD4006B Types, "COS/MOS 18-Stage Static Shift Register".

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