CMOS isolation cell for embedded memory in power failure...

Details CMOS isolation cell for embedded memory in power failure... CMOS isolation cell for embedded memory in power failure...

2005-12-20

2005-12-20

Phan, Trong (Department: 2827)

Static information storage and retrieval

Hardware for storage elements

C365S226000

Reexamination Certificate

active

06977833

ABSTRACT:
An embedded memory on an integrated circuit chip is capable of being isolated from other on chip and off chip circuitry during power failure modes on the integrated circuit chip. The embedded memory preferably has its own external power supply. When power on chip fails or falls below a threshold level, input to and output from the embedded memory is prohibited by CMOS isolation cells. The CMOS isolation cells are controlled by enable signals and the power level of other power supplies within the integrated circuit.

REFERENCES:
patent: 5978262 (1999-11-01), Marquot et al.
patent: 6205078 (2001-03-01), Merritt
patent: 6650589 (2003-11-01), Clark
patent: 6781915 (2004-08-01), Arimoto et al.

Affiliated with

Also associated with

Rating

CMOS isolation cell for embedded memory in power failure... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS isolation cell for embedded memory in power failure..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS isolation cell for embedded memory in power failure... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3473936