CMOS inverter having temperature and supply voltage variation co

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

307451, 307497, 307263, 307310, H03K 1714

Patent

active

048945617

ABSTRACT:
A semiconductor integrated circuit comprises a pair of P-channel and N-channel MOS output transistors connected in series between a power source voltage node and a ground node, a first logic circuit for controlling a gate potential of the P-channel MOS output transistor, a first current control circuit for controlling a current flowing into a ground potential path of the first logic circuit, a second logic circuit for controlling a gate potential of the N-channel MOS output transistor, a second current control circuit for controlling a current flowing into a power source potential path of the second logic circuit, and the first and second current control circuits having a current-temperature characteristic and a current-power source voltage characteristic which are inversely proportional to those of the MOS output transistors. With such an arrangement, the power source voltage dependency and the temperature dependency of the MOS output transistors are cancelled out by the control currents of the first and second current control circuits. Thus, the output voltage of the output circuit depends little on the change of the power source voltage and the operating temperature.

REFERENCES:
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4593203 (1986-06-01), Iwahashi et al.
patent: 4645948 (1987-02-01), Morris et al.
patent: 4736123 (1988-04-01), Miyazawa et al.
patent: 4749882 (1988-06-01), Morgan
patent: 4760292 (1988-07-01), Bach
patent: 4785203 (1988-11-01), Nakamura
patent: 4792704 (1988-12-01), Lobb et al.
patent: 4797579 (1989-01-01), Lewis
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 4827159 (1989-05-01), Naganuma
Wang et al., "A 21-ns 32K.times.8 CMOS Static RAM with a Selectively Pumped p-Well Array," IEEEE Journal of Solid State Circuits, vol. SC-22 No. 5, Oct. 1987, pp. 704-711.
Gubbels et al., "A 40 ns/100-pf Low-Power Full-CMOS 256K(32K.times.8) SCAM," IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 741-747.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

CMOS inverter having temperature and supply voltage variation co does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS inverter having temperature and supply voltage variation co, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS inverter having temperature and supply voltage variation co will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1336624

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.