Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-06-07
2001-06-12
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S552000
Reexamination Certificate
active
06246268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to signal detection and in particular an integrated circuit signal detector for a data communication system.
2. Description of Related Art
The detection of signals at a specific frequency with a specific signal strength is often required in a data communication system. As an example, in an Ethernet system certain signals with an amplitude greater than 200 mv are required to be detected before a link between two stations can be established. It is desirable to have this detection capability implemented in an integrated circuit using typical digital circuit process steps.
In U.S. Pat. No. 5,940,400 (Eastmond et al.) a method and device is directed to provide collision presence detection in wireless intensity modulated binary coded transceivers. A measurement of the degree of correlation which exists between a transmitted signal and a received signal provides the basis for collision detection. In U.S. Pat. No. 5,717,720 (Jackson et al.) is directed to digital data receivers, methods and circuitry for differentiating between signals and data packets of varying protocols and frequencies transferred over a digital burst mode communications system. U.S. Pat. No. 5,199,049 (Wilson) is directed to a digital squelch circuit for detecting valid data signals in a burst mode communication system, e.g. a packet based LAN. A counter is started in a squelch circuit and input signals are detected at various interval of the counter. If there is an input signal transition a predetermined number of times as measured by the counter, the input signal is defined as valid.
A typical implementation of a signal detector is shown in
FIG. 1. A
differential input
10
is connected to a high pass filter
11
. The high pass filter
11
comprising circuit elements C
1
, C
2
, R
1
and R
2
is connected to a first operational amplifier
12
connected in differential mode. The output of the first operational amplifier
12
is connected to a low pass filter
13
comprising circuit elements C
3
, C
4
, R
3
and R
4
. The low pass filter
13
is further connected to a second operational amplifier
14
connected in differential mode. In the output circuitry of the second operational amplifier
14
is an offset circuit
15
comprising resistors R
5
and R
6
and current sources J
1
and J
2
. The offset is determined by the current from current source J
2
flowing through R
6
. A comparator
16
is connected to the offset circuitry
15
such that a signal from second operational amplifier
14
must be larger than the offset voltage to produce a signal at the output
17
of the comparator
16
.
If the cutoff frequency of the high pass filter
11
is lower than the cutoff frequency of the low pass filter
13
, then a signal at the differential input
10
with a frequency between the two cut off frequencies will produce an output from the second operational amplifier
14
. If the input signal has sufficient amplitude to overcome the offset voltage produced by the offset circuitry
15
, then the comparator will produce a pulse at the output
17
.
A problem with the circuitry of
FIG. 1
is that it is difficult to integrate the circuitry into a chip containing digital circuitry. Capacitors C
1
and C
2
are connected in a “floating” configuration where they are not directly connected to ground or a circuit bias. Using a CMOS integrated circuit processes it is not easy to implement these capacitors. Either special silicon wafer steps are required that are not a part of typical CMOS digital circuit process steps, or a big area is required to facilitate a metal layer to metal layer capacitors. A second problem results from the need for multiple stages requiring relatively complicated circuitry in each stage which increases the cost of design and manufacture but also has a tendency to limit the circuit performance at high frequency signals.
OBJECTS OF THE INVENTION
It is an object of the present invention to produce a signal detector suitable for use in communication systems that can detect signals at a specific frequency and having a specific strength.
It is another an object of the present invention to provide a signal detector that can be integrated into a CMOS digital integrated circuit using typical CMOS process steps and requiring a small area for implementation.
It is further an object of the present invention to provide a detection circuit with relatively few components and having minimal effect on the performance of processing high frequency signals.
SUMMARY OF THE INVENTION
In the present invention a single stage circuit is used to filter out signals of all frequencies except for an input signal with a specific frequency. The single stage circuit also produces an offset voltage to be used by a subsequent comparator circuit to determine the strength of the signal with the specific frequency. The single stage circuit comprises two transistors operating in parallel and receiving a differential signal. Each transistor has a high pass filter in the source circuitry and a low pass filter in the drain circuitry. The two filters are designed such that the cut off frequency of the high pass filter is below the cut off frequency of the low pass filter which allows a specific frequency from the input to be amplified through to the output. The output is derived in the drain circuitry of the two transistors in such a way that an offset voltage is presented to a comparator connected to the output. The offset voltage allows the comparator to detect a signal of a specific frequency and at a specific strength at the output of the two transistors which is higher than the offset voltage
The low pass and high pass filters are formed by using semiconductor capacitors. The capacitors are formed from CMOS transistors where the source and drain are connected together and the capacitance is formed from the gate to source. The gate of the CMOS capacitors is connected to signal nodes and the drain-source connection of the capacitors is connected to the source bias of the single stage circuitry.
REFERENCES:
patent: 4398154 (1983-08-01), Lee
patent: 4801827 (1989-01-01), Metz
patent: 5199049 (1993-03-01), Wilson
patent: 5283483 (1994-02-01), Laber et al.
patent: 5717720 (1998-02-01), Jackson et al.
patent: 5940400 (1999-08-01), Eastmond et al.
Ackerman Stephen B.
Janofsky Eric B.
Marvell International Ltd.
Saile George O.
Tran Toan
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